The presentation of logic circuit`s Verilog description through linear description

Pavel Yu. Vasilyan

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Title: The presentation of logic circuit`s Verilog description through linear description

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ISSN:

0131-4645

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Տրամաբանական սխեմայի Verilog լեզվով գրառման ներկայացումը տողային նկարագրությամբ

Coverage:

86-90

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Изд-во НАН РА

Date created:

2001-10-10

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pdf

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oai:arar.sci.am:258406

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ՀՀ ԳԱԱ Հիմնարար գիտական գրադարան

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Mathematics Վասիլյան Պ. Յու.

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Digital Library > Articles

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Dec 8, 2023

In our library since:

Jul 24, 2020

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https://arar.sci.am/publication/281466

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ՀՀ ԳԱԱ Շարունակական հրատարակություններ

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The presentation of logic circuit`s Verilog description through linear description	Dec 8, 2023

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