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Via-contact etch process step is traditionally considered as one of the most technically difficult steps in semiconductor processing. A variety of via patterns characterized by different densities are used as text structures to reach a targeted etch rate, targeted feature profile (sidewall slope, bottom flatness, corner rounding, etc.) and electrical as well as reliability targets. One of the most serious problems is determination of the process recipe window, which covers all issues associated with the pattern density variations. A cause of this problem is in well-known microloading phenomenon [1] (MP), which is an across-layout steady state variation in concentration of neutral species participating in etching reactions. This variation is caused by a variation in pattern density which generates a variation in radical consumption. MP manifests itself when neutral diffusion is not fast enough to alleviate concentration gradients. Etch rate of any arbitrary via is characterized by a global pattern density (PD), i.e., a number of vias belonging to the layout segment of the size of the mean free path l of gas species, as well as by a local PD. While the former factor is responsible for the global radical density variation across the layout the last one, determined by the feature aspect ratio (AR), introduces an additional variation in radical flux numbers consumed by etch reactions inside via.

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