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Title:
SHORT OUTLINE OF SILICON MOS-LIKE STRUCTURES FABRICATION TECHNIQUES, CVC AND NOISE MEASUREMENTS
Creator:
F. V. Gasparyan ; S. V. Melkonyan ; H. V. Asriyan ; C. E. Korman ; B. Noaman ; A. H. Arakelyan ; A. A. Shatvetyan ; A. M. Avetisyan
Corporate Creators:
Yerevan State University ; The George Washington University, Washington DC, USA ; "Transistor Plus" LLC, Yerevan, Armenia
Subject:
Physics ; Electronic structure and electrical properties of surfaces
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Abstract:
The main trends in development of modern ICs (particularly employing MOS/CMOS structures) are related with decreasing of the integrated structures’ geometrical sizes, increasing of the integration density, decreasing of the power consumption, and increasing of the signal/noise ratio. As the wanted signal level is impossible to increase up to some certain critical level, there is a need to decrease internal noise level. In order to tackle the problem several methods are in use. Recently, a variation of MOS structures gate materials’ composition and structure has been successfully utilized [1]. In this article we present a short outline of fabrication technology, peculiarities of the current-voltage characteristics (CVC), and low-frequency noises of experimental samples of silicon MOS-like structures with tungsten (W), chromium (Cr), and iron (Fe) metallic contacts, which were prepared to estimate impact of phonons interface percolation dynamics on 1/f noise in semiconductor micro- and opto-electronic devices [2,3] .
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